Main Components of a Computer

Processor (CPU):

ž Controls computer operations

ž Performs data processing functions

ž Runs under direction of the Operating System

ž Can only communicate via memory (registers)

Main Memory (RAM):

ž Stores data and programs

ž Typically volatile (loses contents when power removed)

ž Read-Write

ž "Real Memory" (as opposed to Virtual Memory)

ž "Primary Storage"

Cache Memory (internal & external):

ž memory between systems

ž a form of buffering

ž holds most recently used data

ž holds most frequently used data

ž holds data likely to be used next

I/O Modules (Input/Output):

ž Move data between CPU and external environment

ž Usually have internal buffers

ž Buffers are temporary storage for data pending release or processing

System Interconnection:

ž Structures and mechanisms to provide communications between processors, main memory, cache and I/O modules

REGISTERS

Registers are high-speed storage memory within the CPU itself, a level of memory that is much faster and smaller than Main Memory

The primary purpose of registers fall into 4 categories:

INPUT: holds data pending CPU processing (buffer)

OUTPUT: holds data the CPU has finished with (buffer)

PROCESS: data being processed, operational

ADDRESS: memory location or I/O device

Typically, a CPU makes use of 2 internal types of Registers.

MAR Memory Address Register

ž Contains ADDRESS for next read/write operation

MBR Memory Buffer Register

ž Contains actual data to be written (flushed) back to main memory, or

ž Receives (read operation) data from main memory

I/O AR I/O Address Register

ž Specifies particular I/O device to read from/write to

I/O BR I/O Buffer Register

ž For exchange of data between I/O modules and CPU

A memory module consists of a set of locations defined by sequentially numbered addresses.

Each location contains a binary number

- could be data or instructions

	CPU
		MAR
PC
		MBR
		I/O AR
IR
		I/O BR

PROCESS REGISTERS

There are 2 categories of these registers ..

USER VISIBLE Registers

ž Assembly language

ž Machine language (native code)

ž Programmers able to control the system

ž Debug style programs

CONTROL & STATUS Registers

ž Used by processor to control system

ž Some priviledged O/S routines can access these to control execution of programs

ž Programmers unable to access to control the system

Not always clearly defined - there are different implementations on different CPUs

USER VISIBLE REGISTERS

DATA Registers

ž Can be assigned to a variety of functions

ž Often available for general use by the O/S and programmers

ž Some may be dedicated for use by the CPU (eg: for FP - floating point - results)

ADDRESS Registers

ž Main Memory addresses of data and instructions

ž Can contain portions of addresses used in the calculation of complete addresses, known as the Base Value

INDEX Registers

ž Contains portions of addresses to add to the Base Value to get the effective address

ž Known as the Offset to the Base

SEGMENT Pointers

ž Used for segmented addresses

ž Could be multiple registers used to store addresses

STACK Pointers

ž Initially points to top of the stack

ž Allows for instructions with no address field (eg: PUSH and POP)

FLAG Pointers

ž Condition codes

ž Decisions will be made based on register state

ž Bit set by processor as a result of operations

ž Is result a signed number (+ve), (-ve) ?

ž Is there a register overflow ?

ž Loop control at zero ?

ž Should interrupts be serviced ?

CONTROL & STATUS Registers

These registers are usually not visible to the user (programmers cannot access them to monitor state of processes)

PROGRAM Counter (PC)

ž Contains addresses of instructions to be fetched

INSTRUCTION Register (IR)

ž Contains instructions most recently fetched

PROGRAM Status Word (PSW)

ž Most systems contain registers that contain internal flag/condition codes similar to the User-Visible Flag Register

ž These are registers to contain status information

ž Sign, Zero, Carry, Equal, Overflow, Interrupt Enable/Disable, Supervisor

There are 2 techniques used to enable the CPU to determine whether a Device Controller has finished a task.

POLLING

- The CPU regularly checks the Status Registers of each device to see if it has completed an operation or needs attention (eg: if an error has occured).

INTERRUPTS

- The Device Controller sends a signal to the CPU

Interrupt Service Routines are special purpose programs to determine what should be done when an interrupt signal is received.

(Sometimes called an Interrupt Handler)

Using interrupts is more efficient because the CPU is only involved when it is needed.

When an interrupt signal is detected, the CPU hardware performs 2 main actions.

ž Automatically suspends the current process and saves its details in an area of memory called the STACK

ž Loads the address of the interrupt handler and runs the service routine

The service routine takes control of the CPU and could be implemented in software or firmware.

CLASSES of INTERRUPTS

There are 2 types of interrupts in use within a system

ž HARDWARE

ž Mechanisms, usually tracks on the motherboard that can have voltages applied, or other methods to signal the request to the CPU or its Interrupt Controller

ž SOFTWARE

ž Operating System interrupts (may be a high number of them in use) that enable programmers to request O/S action (eg: display on the screen, print, storage requests, etc)

HARDWARE INTERRUPTS

PROGRAM

ž Generated as a result of instruction execution

TIMER

ž Allows the processor to do a range of tasks, such as housekeeping and making sure that quantums are not exceeded

I/O (Input/Output)

ž Generated by I/O controllers

ž Enable external components to request the CPU to do something or supply data

ž Usually the only method of communication by external devices

HARDWARE Failure

ž Memory parity errors

ž Power problems